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| Micrel, Inc. QUAD MULTIPLEXER/LATCH DESCRIPTION SY100S355 SY100S355 FEATURES s s s s s s s s s s Max. propagation delay of 1100ps Max. enable to output delay of 1400ps IEE min. of -80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity Internal 75K input pull-down resistors 50% faster than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S355 offers four transparent latches with differential outputs and is designed for use in highperformance ECL systems. The Select inputs (S0, S1) select one of the two sources of input data (D0 or D1) to the latch. The Select inputs can also force the outputs to a logic LOW when the latch is in the transparent mode. The latches are in the transparent mode when both Enables (E1, E2) are at a logic LOW state. In the transparent mode, the Select inputs can pass an input logic HIGH from D0 or D1 to the output. If the Select inputs are tied together, then input data from either D0 or D1 is always passed through. A rising edge on either Enable input will latch the outputs with the most recent data at the latch inputs being stored. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75K pull-down resistors. BLOCK DIAGRAM S0 S1 D0a D D1a E CD D0b D D1b E CD D0c D D1c E CD D0d D D1d E E1 E2 MR CD Qd Q Qd Qc Q Qc Qb Q Qb Qa Q Qa M9999-032406 hbwhelp@micrel.com or (408) 955-1690 Rev.: H Amendment: /0 1 Issue Date: March 2006 Micrel, Inc. SY100S355 PACKAGE/ORDERING INFORMATION D0b D1a VEES D1b D0a Qa Qa Ordering Information Part Number 4 3 Qb Qb VCCA VCC VCC Qc Qc 11 10 9 8 7 6 5 S0 S1 VEE VEES MR E1 E2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Top View PLCC J28-1 Package Type F24-1 F24-1 J28-1 (1) Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Package Marking SY100S355FC SY100S355FC SY100S355JC SY100S355JC SY100S355JZ with Pb-Free bar-line indicator SY100S355JZ with Pb-Free bar-line indicator Lead Finish Sn-Pb Sn-Pb Sn-Pb Sn-Pb Matte-Sn Matte-Sn SY100S355FC SY100S355FCTR(1) SY100S355JC SY100S355JCTR SY100S355JZ (2) 2 1 28 27 26 J28-1 J28-1 J28-1 SY100S355JZTR(1, 2) Notes: D0c D1c D0d VEES D1d Qd Qd 28-Pin PLCC (J28-1) E1 MR VEE S1 E2 S0 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. D0c D1c D0d D1d Qd Qd 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 D1b D0b D1a D0a Qa Qa 13 7 8 9 10 11 12 Qc VCC VCCA Qc 24-Pin Cerpack (F24-1) M9999-032406 hbwhelp@micrel.com or (408) 955-1690 Qb Qb 2 Micrel, Inc. SY100S355 PIN NAMES Pin E1 - E2 S0, S1 MR Dna - Dnd Qa - Qd Qa -- Qd VEES VCCA Function Enable Inputs (Active LOW) Select Inputs Master Reset Data Inputs Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs TRUTH TABLE(1) Inputs MR H L L L L L L L L L L E1 X L L L L L L L L H X E2 X L L L L L L L L X H S1 X H H L L L H H H X X S0 X H H L L H L L L X X D1X X H L X X X H X L X X D0X X X X H L X X H L X X Outputs QX H L H L H H L L QX L H L H L L H H H L Latched Latched NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH Parameter Input HIGH Current S0, S1 E1, E2 Dna, Dnd MR Power Supply Current Min. -- -- -- -- -80 Typ. -- -- -- -- -57 Max. 220 350 340 430 -40 mA Inputs Open Unit A Condition VIN = VIH (Max.) IEE M9999-032406 hbwhelp@micrel.com or (408) 955-1690 3 Micrel, Inc. SY100S355 AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dna - Dnd to Output (Transparent Mode) Propagation Delay S0, S1 to Output (Transparent Mode) Propagation Delay E1, E2 to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time Dna - Dnd S0, S1 MR (Release Time) Hold Time Dna - Dnd S0, S1 Pulse Width LOW, E1, E2 Pulse Width HIGH, MR Min. 300 Max. 1200 TA = +25C Min. 300 Max. 1200 TA = +85C Min. 300 Max. 1200 Unit ps Condition 300 1500 300 1500 300 1500 ps 300 300 300 1500 1200 900 300 300 300 1500 1200 900 300 300 300 1500 1200 900 ps ps ps ps 700 1200 1000 400 400 1000 1000 -- -- -- -- -- -- -- 700 1200 1000 400 400 1000 1000 -- -- -- -- -- -- -- 700 1200 1000 400 400 1000 1000 -- -- -- ps -- -- -- -- ps ps tH tPW (L) tPW (H) PLCC VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dna - Dnd to Output (Transparent Mode) Propagation Delay S0, S1 to Output (Transparent Mode) Propagation Delay E1, E2 to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time Dna - Dnd S0, S1 MR (Release Time) Hold Time Dna - Dnd S0, S1 Pulse Width LOW, E1, E2 Pulse Width HIGH, MR Min. 300 Max. 1100 TA = +25C Min. 300 Max. 1100 TA = +85C Min. 300 Max. 1100 Unit ps Condition 300 1400 300 1400 300 1400 ps 300 300 300 1400 1100 900 300 300 300 1400 1100 900 300 300 300 1400 1100 900 ps ps ps ps 700 1200 1000 300 300 1000 1000 -- -- -- -- -- -- -- 4 700 1200 1000 300 300 1000 1000 -- -- -- -- -- -- -- 700 1200 1000 300 300 1000 1000 -- -- -- ps -- -- -- -- ps ps tH tPW (L) tPW (H) M9999-032406 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY100S355 TIMING DIAGRAMS 0.7 0.1 ns -0.95V Dna - Dnd S0, S1 -1.69V tpw -0.95V ENABLE TRANSPARENT tPHL, tPLH LATCHED tPHL, tPLH TRANSPARENT -1.69V tPHL, tPLH 80% 50% 20% tTHL, tTLH OUTPUT Enable Timing RESET TIMING DATA ENABLE TRANSPARENT LATCHED TRANSPARENT tR RELEASE TIME RESET/SET tPHL, tPLH tpw tPHL, tPLH tPHL, tPLH OUTPUT Reset Timing M9999-032406 hbwhelp@micrel.com or (408) 955-1690 5 Micrel, Inc. SY100S355 TIMING DIAGRAMS -0.95V S0, S1 tS tH 50% -1.69V -0.95V DATA tS tH 50% -1.69 -0.95V E1, E2 50% -1.69V Data Set-up and Hold Times Notes: 1. VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND 2. ts is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. M9999-032406 hbwhelp@micrel.com or (408) 955-1690 6 Micrel, Inc. SY100S355 24-PIN CERPACK (F24-1) Rev. 03 M9999-032406 hbwhelp@micrel.com or (408) 955-1690 7 Micrel, Inc. SY100S355 28-PIN PLCC (J28-1) Rev. 03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL USA + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-032406 hbwhelp@micrel.com or (408) 955-1690 8 |
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